Function core::arch::riscv64::sfence_w_inval
source · pub unsafe fn sfence_w_inval()
🔬This is a nightly-only experimental API. (
stdsimd
#27731)Available on RISC-V RV64 only.
Expand description
Generates the SFENCE.W.INVAL
instruction
This instruction guarantees that any previous stores already visible to the current RISC-V hart
are ordered before subsequent SINVAL.VMA
instructions executed by the same hart.